1. Field of Invention
The present invention relates generally to semiconductor devices, and, more particularly, to input/output structures for protecting-devices from electrical transients and having an improved ability to withstand the effects of substrate noise.
2. Description of the Related Art
Substrate noise in semiconductor devices, such as CMOS devices, can have several non-desirable effects. In particular, a common failure mode in semiconductor products of the type that use relatively high voltage pins, such as programming voltage pins Vpp, is a so-called electrical over stress (EOS) failure. The EOS failure involves abnormal, high-current events which can damage the device and, which is due in some cases to an undesirable turn on and conduction of an electrostatic discharge (ESD) protection structure used in the semiconductor product. One cause of the undesired turn on and conduction of the ESD protection device stems from substrate noise in the vicinity of the ESD device.
In a common ESD device configuration, a grounded-gate n-channel field effect transistor (FET) is used as the primary ESD protection device. The grounded-gate FET has its drain region connected to an input/output pad of the product, and further has its gate and source tied to ground (Vss). During normal operation of the device, the FET presents a high-impedance path from the pad to ground. It therefore has no significant effect in the normal operation of the device. However, during ESD events, the grounded-gate FET relies on a so-called xe2x80x9csnapbackxe2x80x9d mechanism to enter a low impedance state to remove excess and often dangerous ESD charge from the critical node. In xe2x80x9csnapbackxe2x80x9d mode, the grounded-gate FET operates as a parasitic lateral npn bipolar transistor to provide the low-impedance path between the I/O pad and ground. Snapback generally occurs when the voltage on the I/O pad increases to a high enough value (e.g., 15 volts for a typical CMOS process) so that the n+ drain/p-substrate junction of the FET breaks down. This breakdown, in-effect, provides the lateral npn bipolar transistor with a base current supplied by holes generated by impact ionization near the drain region of the channel. Conduction stops when the ESD charge has been removed. The FET again assumes a high-impedance state.
A problem arises, however, when using such a FET on a programming pin. Although voltages used for normal programming operations (e.g., where Vpp may be about 13 volts) are not generally high enough to cause the ESD device (e.g., the grounded-gate FET) to snap back, noise can trigger the FET into snapback. Specifically, substrate noise in the vicinity of the source region can provide the difference needed to put the ESD device in the low impedance, snapback mode. Once the grounded-gate FET snaps back, it will continue to conduct, inasmuch as the holding voltage for the FET in snapback is substantially lower than the applied programming voltage Vpp. Substantial currents flow, which may result in a catastrophic failure of the semiconductor product.
Accordingly, there is a need to provide an improved input/output structure, particularly an improved ESD protection device, that minimizes or eliminates one or more of the problems as set forth above.
It is an object of the present invention to provide an input/output structure that improves substrate noise immunity. It is a further object of the present invention to provide an ESD protection device for use on I/O pins which provides improved immunity to undesirable turn on during high voltage data programming operations. It is yet a further object of the present invention to provide an ESD protection device that permits an efficient and compact layout.
To achieve these and other objects, a structure in a semiconductor device comprises (i) a transistor formed in a first region of a first conductivity type, and (ii) a tap region of the first conductivity type. The transistor has a gate, and source and drain regions having a second conductivity type opposite the first conductivity type. The tap region is adjacent to and extends from a selected one of the source and drain regions. The other one of the source and drain regions is connected to an input/output pad, and the selected one of the source and drain regions, the gate, and the tap region are all electrically connected to a common node, preferably Vss. The principal involved is to locally tie both the substrate (via the tap region) and the source (in a preferred embodiment) to the same potential. This configuration improves the ability to withstand the effects of substrate noise. The invention does not completely prevent snap-back, but rather increases the threshold at which this effect takes place.
In a preferred embodiment, the first conductivity type is p-type, and the second conductivity type is n-type wherein the tap region may be formed in two different shapes. In the first preferred embodiment, the n+ source region comprises a plurality of n+ subregions wherein the tap region comprises one or more generally bar shaped subregions disposed in parallel relations relative to the source subregions. In another preferred embodiment, the tap region is generally annular in shape and surrounds the source region.
Devices in accordance with the present invention are less sensitive to substrate noise since the substrate (or well), which preferably is p-type and in which the n-channel ESD protection device is formed, and the source of the ESD protection device, are tied locally, by way of the above-described tap regions, to the same voltage potential. Moreover, in the second preferred embodiment wherein the tap region is generally annular in shape, the placement of the grounded p-type tapping between the source and the gate significantly reduces the ability of the intrinsic lateral npn bipolar transistor to switch on. This effect is also present in the preferred embodiment where the tap region is generally bar shaped, but to a lesser degree. In addition, implementing the present invention requires no changes in the standard fabrication process, which preferably includes CMOS processes. Rather, the present invention may be implemented merely by mask changes, as will become apparent to those of ordinary skill in the art. This invention therefore provides a cost effective solution to the problems described in the Background.